JD：
ASIC或SoC芯片的模块级和顶层级物理验证；
Debug不同foundary（TSMC，SAMSUNG，SMIC）深亚微米先进工艺（7nm, 16nm, 28nm）的DRC, LVS, ANT, ERC, ESD等；
基于物理验证report改进APR flow；
维护tape-out flow；
芯片full-chip tape out;
Requirements：
大学本科以上学历，微电子／电子工程／通信工程等相关专业 ；
相关的物理设计工作经验或tape-out成功经验；
熟悉DRC，LVS、ANT等流程；
熟悉EDA工具，如 ICV，Calibre等；
熟练使用tcl/perl/phython等；
良好的英文沟通能力；
公司简介：
Founded in 2018, founder has 20 years’ IC industry experience, worked for top IC companies like IBM, AMD, Synopsys, Verisilicon, SYNAPSE and Intel as leader, has long-term, solid and positive relationships with all patterners. And the team members most have 10+ years’ IC design experience, merging with the fastest growing technology both in ASIC and SOC field, patterner including AMD, ADI，GlobalFoundries, HiGon, ZTE，GPT, SYNAPSE，MICROPILOT…
Mass production including diverse productions: 7nm/14nm GPU design chip, 28nm high-end graphic chip, 28nm mobile phone chip, 28nm low-power graphic chip, 40nm networking chipset, 55nm mobile chip… we also provide professional, effective and practical consulting service for newly established company.
Now we have Beijing, Shanghai, Nanjing, Chengdu sites, to support flexible and high-efficiency working model both for patterner and employee.