Job Description:
- Block, IP and VLSI top level DFT implementation (MBIST, Scan, Boundary Scan, analog/IP and RF test etc.), SoC database DFT coding and integration;
- Participate in SoC test spec/plan definition, complete DFT design document and signoff review checklists;
- SoC DFT quality sign-off; DFT SDC and FV constraint generation and release; ECO and formal check;
- Test patterns/vectors generation and verification, including RTL level, pre&post layout gate level simulation;