主要工作内容:
与顶层架构师合作定义STA目标、低功耗策略等
开发SOC级设计，并保证功能正确
完成RTL综合和质量检查
检查并推动问题解决和质量改进, 包括 RTL 语法检查, 逻辑等价性检查, 跨时钟域设计, 低功耗设计，时序分析等
与后端PD团队合作完成布局布线、时序收敛、低功耗设计验证等工作;
Key Responsibilities:
Work with guideline and architect to define STA target, power strategy, etc.
Develop SOC level design ;
Complete front-end netlisting and quality check
Check and drive issue solving and quality improvement, including RTL syntax check, LEC, CDC, Low power design and STA etc.
Working with physical design team on floorplan, timing closure, etc.
技能与经验要求:
具备较强的电子电路基础
具备较强的分析问题和解决问题的能力
熟悉EDA工具，如DC, Formality, PT
熟悉Linux，脚本者优先，脚本语言包括Perl / tcl / cshell / python。
公司简介：
Founded in 2018, founder has 20 years’ IC industry experience, worked for top IC companies like IBM, AMD, Synopsys, Verisilicon, SYNAPSE and Intel as leader, has long-term, solid and positive relationships with all patterners. And the team members most have 10+ years’ IC design experience, merging with the fastest growing technology both in ASIC and SOC field, patterner including AMD, ADI，GlobalFoundries, HiGon, ZTE，GPT, SYNAPSE，MICROPILOT…
Mass production including diverse productions: 7nm/14nm GPU design chip, 28nm high-end graphic chip, 28nm mobile phone chip, 28nm low-power graphic chip, 40nm networking chipset, 55nm mobile chip… we also provide professional, effective and practical consulting service for newly established company.
Now we have Beijing, Shanghai, Nanjing, Chengdu sites, to support flexible and high-efficiency working model both for patterner and employee.