**Responsibilities**
Define the ADC architecture based on capacitive DAC (SAR) or pipeline
interleave structure.
Implement calibration methodology.
Simulate all the components (blocks and top level), layout critical blocks
Run DRC, LVS, PEX
Tape out and follow up
Test bench qualification
Datasheet writing
Understanding production constrains and ATE
**Requirments**
Experience in analog circuit
Experience in 16+ bit SAR ADC or pipeline flash ADC
Tools: CADENCE front-end and back-end, Mentor-Siemens simulation and
layout verification
Linux based Design
English communication
Plus: proficient with at least 1 scripting language, e.g., Python, TCL
**Company Info**
Zynalog is a fabless startup focus on analog IC design, located in Suzhou, and
with design center in Shanghai
Our company is founded in 2021, the company is young but people inside are
not, 80% of Zynalog members are IC developer with 20+ years’ experience.
We are not looking for employees but friends of similar purpose and interests,
with self-driving working style and has passion in technology.
we pursuit our own dreams, and create value for our stakeholders, customers
and society.