Key Areas of Responsibility
1. Do full custom IC layout, for analog, digital and mix-signal blocks.
2. Hook-up the leaf cells to block level and full-chip level.
3. Optimizing layout and power/ground nets connection.
4. Work with circuit design engineers to solve potential issues such as ESD, Latch-up, timing, noise and so on.
5. Layout verification including LVS, DRC, ERC.
6. Parasitic RC extraction and optimize.
Required knowledge, skills, abilities
1. Familiar with layout design tool and layout verification tool.
2. Good understanding of layout effects on device performance in silicon.
3. Capability of maintaining p-cells, TF, rule files would be a plus.
4. BS or higher in science and/or engineering areas with 1+year IC layout design experience.