职位名称：版图设计工程师
职位描述：
1. 合作完成基于业界先进的CMOS Finfet/FDSOI以及特色成熟工艺下的基础IP库，模拟及混合信号IP，无线射频IP，ASIC定制芯片等的版图正向开发；
2. 完成DRC/LVS/DFM等sign-off物理验证，寄生参数的抽取及设计优化；
3. 根据公司设计流程产生流片数据包。
职位要求：
1. 微电子/电子工程/物理电子等相关专业本科及以上学历；
2. 扎实掌握半导体器件，制造工艺，模拟电路原理等相关基础知识；
3. 符合以下条件者优先：
硕士学历
熟悉Unix/Linux系统，Cadence/Mentor IC开发工具及流程
Perl/Tcl/Skill脚本编程基础
4. 富有事业心和团队合作精神，良好的中英文听说读写能力。
工作地点：成都/海口
Title: Layout Design Engineer
Responsibilities:
1. Collaborate on layout design of foundation IP library, Analog and Mix-signal IP, Wireless RF IP and ASIC chips base on most advanced CMOS Finfet/FDSOI and specialized mature processes.
2. Finish sign-off verification (DRC/LVS/DFM…), parasitic extraction, and layout optimization.
3. Generate IP tape-out kits following design flow.
Requirements:
1. Bachelor's or above degree in Microelectronics, EE, Physical Electronics or related major.
2. Solid understanding of semiconductor devices, IC manufacturing, and analog circuit principles.
3. Candidates meeting the following criteria are preferred:
Master degree
Be familiar with Unix/Linux OS, experiences in Cadence/Mentor EDA tools and flow
Scripting skills (Perl/Tcl/Skill)
4. Self-motivated and a good team player. Good communication skills in both Chinese and English in either listening, speaking, reading or writing.
Location: Chengdu/Haikou